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K6R1016V1C-C/C-L, K6R1016V1C-I/C-P
Document Title
64Kx16 Bit High-Speed CMOS Static RAM(3.3V Operating) Operated at Commercial and Industrial Temperature Ranges.
for AT&T CMOS SRAM
Revision History
Rev. No. Rev. 0.0 Rev. 1.0 History Initial release with Preliminary. Release to Final Data Sheet. 1.1. Delete Preliminary. 1.2. Changed DC characteristics. Item ICC 12ns 15ns 20ns Added 48-fine pitch BGA. Changed device part name for FP-BGA. Item Previous Symbol Z ex) K6R1016V1C-Z -> K6R1016V1C-F Changed device ball name for FP-BGA. Previous I/O1 ~ I/O8 I/O9 ~ I/O16 1. Added 10ns speed for FP-BGA only. 2. Changed Standby Current. Item Previous Standby Current(Isb1) 0.3mA 3. Added Data Retention Characteristics. Draft Data Aug. 5. 1998 Sep. 7. 1998 Remark Preliminary Final
Previous 85mA 83mA 80mA
Changed 95mA 93mA 90mA Sep. 17. 1998 Nov. 5. 1998 Changed F Final Final
Rev. 2.0 Rev. 2.1
Rev. 2.2
Dec. 10. 1998 Changed I/O9 ~ I/O16 I/O1 ~ I/O8 Mar. 2. 1999 Changed 0.5mA
Final
Rev. 3.0
Final
Rev. 3.1 Rev. 3.2
Added 10ns speed for all packages(44SOJ / 44TSOP2 / 48FPBGA) Supply Voltage Change 1. Only 10ns Bin : 3.15V ~ 3.6V 2. The Rest Bin : 3.0V ~ 3.6V VIH/VIL Change Item VIH VIL Previous Min 2.0 -0.5 Max VCC+0.5 0.8 Min 2.0 -0.3 Changed Max VCC+0.3 0.8
Apr. 24. 2000 Aug. 25. 2000
Final Final
Rev. 3.3
Oct. 2. 2000
Final
The attached data sheets are prepared and approved by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserve the right to change the specifications. SAMSUNG Electronics will evaluate and reply to your requests and questions on the parameters of this device. If you have any questions, please contact the SAMSUNG branch office near your office, call or contact Headquarters.
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Revision 3.3 October 2000
K6R1016V1C-C/C-L, K6R1016V1C-I/C-P
FEATURES
* Fast Access Time 10,12,15,20ns(Max.) * Low Power Dissipation Standby (TTL) : 30mA(Max.) (CMOS) : 5mA(Max.) 0.5mA(Max.) L-ver. only Operating * K6R1016V1C-10: 105mA(Max.) K6R1016V1C-12: 95mA(Max.) K6R1016V1C-15: 93mA(Max.) K6R1016V1C-20: 90mA(Max.) * Single 3.3V Power Supply * TTL Compatible Inputs and Outputs * Fully Static Operation - No Clock or Refresh required * Three State Outputs * 2V Minimum Data Retention: L-ver. only * Center Power/Ground Pin Configuration * Data Byte Control: LB: I/O1~ I/O8, UB: I/O9~ I/O16 * Standard Pin Configuration: K6R1016V1C-J: 44-SOJ-400 K6R1016V1C-T: 44-TSOP2-400BF K6R1016V1C-F: 48-Fine pitch BGA with 0.75 Ball pitch
for AT&T CMOS SRAM
64K x 16 Bit High-Speed CMOS Static RAM(3.3V Operating)
GENERAL DESCRIPTION
The K6R1016V1C is a 1,048,576-bit high-speed Static Random Access Memory organized as 65,536 words by 16 bits. The K6R1016V1C uses 16 common input and output lines and has at output enable pin which operates faster than address access time at read cycle. Also it allows that lower and upper byte access by data byte control (UB, LB). The device is fabricated using SAMSUNGs advanced CMOS process and designed for high-speed circuit technology. It is particularly well suited for use in high-density high-speed system applications. The K6R1016V1C is packaged in a 400mil 44-pin plastic SOJ or TSOP2 forward or 48-Fine pitch BGA.
FUNCTIONAL BLOCK DIAGRAM
Clk Gen.
A0 A1 A2 A3 A4 A5 A6 A7 A8 I/O1~I/O8 I/O9~I/O16
ORDERING INFORMATION
K6R1016V1C-C10/C12/C15/C20 Commercial Temp. Industrial Temp. K6R1016V1C-I10/I12/I15/I20
Pre-Charge Circuit
Row Select
Memory Array 512 Rows 128x16 Columns
PIN FUNCTION
Pin Name Data Cont. Data Cont. Gen. CLK
A9 A10 A11 A12 A13 A14 A15
Pin Function Address Inputs Write Enable Chip Select Output Enable Lower-byte Control(I/O1~I/O8) Upper-byte Control(I/O9~I/O16) Data Inputs/Outputs Power(+3.3V) Ground No Connection
I/O Circuit & Column Select
A0 - A15 WE CS OE LB UB I/O1 ~ I/O16
WE OE UB LB CS
VCC VSS N.C
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Revision 3.3 October 2000
K6R1016V1C-C/C-L, K6R1016V1C-I/C-P
PIN CONFIGURATION(TOP VIEW)
1 2 3
for AT&T CMOS SRAM
4 5 6
A0 A1 A2 A3 A4 CS I/O1 I/O2 I/O3
1 2 3 4 5 6 7 8 9
44 A15 43 A14 42 A13 41 OE 40 UB 39 LB 38 I/O16 37 I/O15 36 I/O14
D Vss I/O4 N.C A7 I/O12 Vcc C I/O2 I/O3 A5 A6 I/O11 I/O10 B I/O1 UB A3 A4 CS I/O9 A LB OE A0 A1 A2 N.C
I/O4 10 Vcc 11 Vss 12 I/O5 13 I/O6 14 I/O7 15 I/O8 16 WE 17 A5 18 A6 19 A7 20 A8 21 N.C 22
SOJ/ TSOP2
35 I/O13 34 Vss 33 Vcc 32 I/O12 31 I/O11 30 I/O10 29 I/O9 28 N.C 27 A12 26 A11 25 A10 24 A9 23 N.C
H N.C A8 A9 A10 A11 N.C G I/O8 N.C A12 A13 WE I/O16 F I/O7 I/O6 A14 A15 I/O14 I/O15 E Vcc I/O5 N.C N.C I/O13 Vss
48-CSP
ABSOLUTE MAXIMUM RATINGS*
Parameter Voltage on Any Pin Relative to VSS Voltage on VCC Supply Relative to VSS Power Dissipation Storage Temperature Operating Temperature Commercial Industrial Symbol VIN, VOUT VCC Pd TSTG TA TA Rating -0.5 to 4.6 -0.5 to 4.6 1 -65 to 150 0 to 70 -40 to 85 Unit V V W C C C
* Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operating sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
RECOMMENDED DC OPERATING CONDITIONS (TA= 0 to 70C)
Parameter Supply Voltage Supply Voltage Ground Input High Voltage Input Low Voltage Symbol VCC VCC
(1) (2)
Min 3.15 3.0 0 2.0 -0.3(4)
Typ 3.3 3.3 0 -
Max 3.6 3.6 0 VCC+0.3 0.8
(3)
Unit V V V V V
VSS VIH VIL
(1) For K6R1016V1C-10 only. (2) For all speed grades except K6R1016V1C-10. (3) VIH(Max) = VCC + 2.0V a.c(Pulse Width 8ns) for I 20mA (4) VIL(Min) = -2.0V a.c(Pulse Width 8ns) for I 20mA.
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Revision 3.3 October 2000
K6R1016V1C-C/C-L, K6R1016V1C-I/C-P
*DC
for AT&T CMOS SRAM
AND OPERATING CHARACTERISTICS*(TA=0 to 70C, Vcc=3.3V+0.3V/-0.15V, unless otherwise specfied)
Parameter Symbol ILI ILO ICC Test Conditions VIN=VSS to VCC CS=VIH or OE=VIH or WE=VIL VOUT=VSS to VCC Min. Cycle, 100% Duty CS=VIL, VIN = VIH or VIL, IOUT=0mA 10ns 12ns 15ns 20ns Min -2 -2 Normal L-Ver. 2.4 Max 2 2 105 95 93 90 30 5 0.5 0.4 V V mA mA Unit A A mA
Input Leakage Current Output Leakage Current Operating Current
Standby Current
ISB ISB1
Min. Cycle, CS=VIH f=0MHz, CS VCC-0.2V, VINVCC-0.2V or VIN 0.2V IOL=8mA IOH=-4mA
Output Low Voltage Level Output High Voltage Level
VOL VOH
* The above parameters are also guaranteed at industrial temperature range.
CAPACITANCE*(TA=25C, f=1.0MHz)
Item Input/Output Capacitance Input Capacitance
* Capacitance is sampled and not 100% tested.
Symbol CI/O CIN
Test Conditions VI/O=0V VIN=0V
MIN -
Max 8 6
Unit pF pF
AC CHARACTERISTICS(TA=0 to 70C, Vcc=3.3V+0.3V/-0.15V, unless otherwise noted.)
TEST CONDITIONS*
Parameter Input Pulse Levels Input Rise and Fall Times Input and Output timing Reference Levels Output Loads
* The above test conditions are also applied at industrial temperature range.
Value 0V to 3V 3ns 1.5V See below
Output Loads(A)
Output Loads(B) for tHZ, tLZ, tWHZ, tOW, tOLZ & tOHZ RL = 50 +3.3V
DOUT
VL = 1.5V
ZO = 50 30pF* DOUT
319
353
5pF*
* Capacitive Load consists of all components of the test environment.
* Including Scope and Jig Capacitance
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Revision 3.3 October 2000
K6R1016V1C-C/C-L, K6R1016V1C-I/C-P
READ CYCLE*
Parameter Read Cycle Time Address Access Time Chip Select to Output Output Enable to Valid Output UB, LB Access Time Chip Enable to Low-Z Output UB, LB Enable to Low-Z Output Output Enable to Low-Z Output Chip Disable to High-Z Output Output Disable to High-Z Output UB, LB Disable to High-Z Output Output Hold from Address Change Chip Selection to Power Up Time Chip Selection to Power DownTime Symbol tRC tAA tCO tOE tBA tLZ tBLZ tOLZ tHZ tOHZ tBHZ tOH tPU tPD K6R1016V1C-10 Min 10 3 0 0 0 0 0 3 0 Max 10 10 5 5 5 5 5 10 K6R1016V1C-12 Min 12 3 0 0 0 0 0 3 0 Max 12 12 6 6 6 6 6 12
for AT&T CMOS SRAM
K6R1016V1C-15 Min 15 3 0 0 3 0 Max 15 15 7 7 7 7 7 15 K6R1016V1C-20 Min 20 3 0 0 3 0 Max 20 20 9 9 9 9 9 20 Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns
* The above parameters are also guaranteed at industrial temperature range.
WRITE CYCLE*
Parameter Write Cycle Time Chip Select to End of Write Address Set-up Time Address Valid to End of Write Write Pulse Width(OE High) Write Pulse Width(OE Low) UB, LB Valid to End of Write Write Recovery Time Write to Output High-Z Data to Write Time Overlap Data Hold from Write Time End Write to Output Low-Z Symbol tWC tCW tAS tAW tWP tWP1 tBW tWR tWHZ tDW tDH tOW K6R1016V1C-10 Min 10 7 0 7 7 10 7 0 0 5 0 3 Max 5 K6R1016V1C-12 Min 12 8 0 8 8 12 8 0 0 6 0 3 Max 6 K6R1016V1C-15 Min 15 9 0 9 9 15 9 0 0 7 0 3 Max 7 K6R1016V1C-20 Min 20 10 0 10 10 20 10 0 0 8 0 3 Max 9 Unit ns ns ns ns ns ns ns ns ns ns ns ns
* The above parameters are also guaranteed at industrial temperature range.
TIMMING DIAGRAMS
TIMING WAVEFORM OF READ CYCLE(1) (Address Controlled, CS=OE=VIL, WE=VIH, UB, LB=VIL
tRC Address tOH Data Out Previous Valid Data tAA Valid Data
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Revision 3.3 October 2000
K6R1016V1C-C/C-L, K6R1016V1C-I/C-P
TIMING WAVEFORM OF READ CYCLE(2) (WE=VIH)
tRC Address tAA tCO tBA UB, LB tBLZ(4,5) OE tOLZ Data out ICC ISB
NOTES(READ CYCLE) High-Z
for AT&T CMOS SRAM
tHZ(3,4,5)
CS
tBHZ(3,4,5)
tOHZ tOE tOH Valid Data
tLZ(4,5) tPU 50% tPD 50%
VCC Current
1. WE is high for read cycle. 2. All read cycle timing is referenced from the last valid address to the first transition address. 3. tHZ and tOHZ are defined as the time at which the outputs achieve the open circuit condition and are not referenced to VOH or VOL levels. 4. At any given temperature and voltage condition, tHZ(Max.) is less than tLZ(Min.) both for a given device and from device to device. 5. Transition is measured 200mV from steady state voltage with Load(B). This parameter is sampled and not 100% tested. 6. Device is continuously selected with CS=VIL. 7. Address valid prior to coincident with CS transition low. 8. For common I/O applications, minimization or elimination of bus contention conditions is necessary during read and write cycle.
TIMING WAVEFORM OF WRITE CYCLE(1) (OE =Clock)
tWC Address tAW OE tCW(3) CS tBW UB, LB tAS(4) WE tDW Data in High-Z tOHZ(6) Data out Valid Data tDH High-Z tWP(2) tWR(5)
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Revision 3.3 October 2000
K6R1016V1C-C/C-L, K6R1016V1C-I/C-P
TIMING WAVEFORM OF WRITE CYCLE(2) (OE =Low fixed)
tWC Address tAW tCW(3) CS tBW UB, LB tAS(4) WE tDW Data in High-Z tWHZ(6) Data out High-Z Valid Data tDH tWP1(2) tWR(5)
for AT&T CMOS SRAM
tOW
(10)
(9)
TIMING WAVEFORM OF WRITE CYCLE(3) (CS=Controlled)
tWC Address tAW tCW(3) CS tBW UB, LB tAS(4) WE tDW Data in tDH tWP(2) tWR(5)
High-Z
tLZ tWHZ(6)
Valid Data
High-Z
Data out
High-Z
High-Z(8)
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Revision 3.3 October 2000
K6R1016V1C-C/C-L, K6R1016V1C-I/C-P
TIMING WAVEFORM OF WRITE CYCLE(4) (UB, LB Controlled)
tWC Address tAW tCW(3) CS tBW UB, LB tAS(4) WE tDW Data in tDH tWP(2) tWR(5)
for AT&T CMOS SRAM
High-Z
Valid Data tBLZ tWHZ(6)
Data out
High-Z
High-Z(8)
NOTES(WRITE CYCLE) 1. All write cycle timing is referenced from the last valid address to the first transition address. 2. A write occurs during the overlap of a low CS, WE, LB and UB. A write begins at the latest transition CS going low and WE going low; A write ends at the earliest transition CS going high or WE going high. tWP is measured from the beginning of write to the end of write. 3. tCW is measured from the later of CS going low to end of write. 4. tAS is measured from the address valid to the beginning of write. 5. tWR is measured from the end of write to the address change. tWR applied in case a write ends as CS or WE going high. 6. If OE, CS and WE are in the Read Mode during this period, the I/O pins are in the output low-Z state. Inputs of opposite phase of the output must not be applied because bus contention can occur. 7. For common I/O applications, minimization or elimination of bus contention conditions is necessary during read and write cycle. 8. If CS goes low simultaneously with WE going or after WE going low, the outputs remain high impedance state. 9. Dout is the read data of the new address. 10. When CS is low: I/O pins are in the output state. The input signals in the opposite phase leading to the output should not be applied.
FUNCTIONAL DESCRIPTION
CS H L L L WE X H X H OE X* H X L LB X X H L H L L L X L H L
* X means Dont Care.
UB X X H H L L H L L Write Read
Mode I/O1~I/O8 Not Select Output Disable High-Z High-Z
I/O Pin I/O9~I/O16 High-Z High-Z
Supply Current ISB, ISB1 ICC
DOUT High-Z DOUT DIN High-Z DIN
High-Z DOUT DOUT High-Z DIN DIN
ICC
ICC
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Revision 3.3 October 2000
K6R1016V1C-C/C-L, K6R1016V1C-I/C-P
DATA RETENTION CHARACTERISTICS*(TA=0 to 70C)
Parameter VCC for Data Retention Data Retention Current Symbol VDR IDR Test Condition CSVCC-0.2V VCC=3.0V, CSVCC-0.2V VINVCC-0.2V or VIN0.2V VCC=2.0V, CSVCC-0.2V VINVCC-0.2V or VIN0.2V Data Retention Set-Up Time Recovery Time tSDR tRDR See Data Retention Wave form(below) Min. 2.0 -
for AT&T CMOS SRAM
Typ. -
Max. 3.6 0.4
Unit V mA
-
-
0.3
0 5
-
-
ns ms
* The above parameters are also guaranteed at industrial temperature range. Data Retention Characteristic is for L-ver only.
DATA RETENTION WAVE FORM
CS controlled
VCC 3.0V tSDR Data Retention Mode tRDR
VIH VDR CSVCC - 0.2V
CS GND
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Revision 3.3 October 2000
K6R1016V1C-C/C-L, K6R1016V1C-I/C-P
PACKAGE DIMENSIONS
44-SOJ-400
for AT&T CMOS SRAM
Units:millimeters/Inches
#44
#23
11.18 0.12 0.440 0.005
10.16 0.400
9.40 0.25 0.370 0.010
0.20 +0.10 -0.05 0.008 +0.004 -0.002 #1 28.98 MAX 1.141 25.58 0.12 1.125 0.005 ( 1.19 ) 0.047 3.76 1.27 MAX ( 0.050 ) 0.148 0.10 MAX 0.004 #22 0.69 MIN 0.027
( 0.95 ) 0.0375
0.43 0.017
+0.10 -0.05 +0.004 -0.002
1.27 0.050
0.71 -0.05 0.028 +0.004 -0.002
+0.10
44-TSOP2-400BF
Units:millimeters/Inches
0~8 0.25 0.010 TYP
#44
#23 0.45 ~0.75 0.018 ~ 0.030
10.16 0.400
11.76 0.20 0.463 0.008
( 0.50 ) 0.020 #1 18.81 MAX 0.741 18.41 0.10 0.725 0.004 1.00 0.10 0.039 0.004 ( 0.805 ) 0.032 0.30 +0.10 -0.05 0.012 +0.004 -0.002 0.80 0.0315 0.05 MIN 0.002 1.20 MAX 0.047 0.10 0.004 MAX #22
0.075 0.125 + 0.035 -
0.005 - 0.001
+ 0.003
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Revision 3.3 October 2000
K6R1016V1C-C/C-L, K6R1016V1C-I/C-P
PACKAGE OUTLINE
Top View Bottom View
for AT&T CMOS SRAM
(Units : millimeter)
B B 6 A #A1 B C D 5 4 B1 0.50
A1 INDEX MARK
3
2
1
0.50
C1 E C1/2 F G H B/2 Detail A A 0.25/Typ. Y 0.80/Typ. Notes. 1. Bump counts: 48(8row x 6column) 2. Bump pitch: (x,y)=(0.75 x 0.75)(typ.) 3. All tolerance are +/-0.050 unless otherwise specified. 4. Typ: Typical 5. Y is coplanarity: 0.08(Max)
Side View
D
C
Min A B B1 C C1 D E E1 E2 Y 5.90 6.90 0.30 0.20 -
Typ 0.75 6.00 3.75 7.00 5.25 0.35 1.05 0.80 0.25 -
Max 6.10 7.10 0.40 1.20 0.30 0.08
C
- 11
Revision 3.3 October 2000
C
0.30 E1 E
E2

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